1. Field of the Invention
The present invention relates to a method of forming an insulating structure including an insulating interlayer and a capping layer, and a method of forming a metal wiring structure through the insulating structure. More particularly, the present invention relates to a method of forming an insulating structure including an insulating interlayer and a capping layer without an interface between the insulating interlayer and the capping layer, and a method of forming a semiconductor device including a metal wiring structure using the insulating structure.
2. Description of the Related Art
As information processing apparatus continue to enjoy widespread use, semiconductor devices included in the information processing apparatus are developed to have ever-increasing response speed and storage capacity. Semiconductor manufacturing technologies continue to advance with improvements in the reliability and degree of integration of the semiconductor devices, as the design rule of the semiconductor devices becomes reduced.
In a conventional semiconductor device, a metal wiring structure is generally formed using aluminum (Al) because aluminum has relatively low contact resistance and aluminum wiring is readily formed under conventional processes. However, as the design rule of the semiconductor device is reduced, aluminum-based wiring is not as advantageous, since it is subject to failures due to resistance-capacitance (RC) delay, electro-migration (EM), stress migration (SC), and the like. In addition, the aluminum wiring may limit the semiconductor device with its relatively low response speed.
Recently, copper (Cu) wiring has become popular for use in the metal wiring structure of a semiconductor device since the copper wiring offers the advantages of relatively low resistance and electro-migration. The copper wirings are generally employed using insulation layers having a low dielectric constant. The insulation layers, commonly including nitride or oxide, are used as an etch stop layer, an insulating interlayer, a capping layer or a spacer in the fabrication process. For example, a silicon nitride layer has a specific dielectric constant of about 8 so that the silicon nitride layer is advantageously used as the etching stop layer, the capping layer or the spacer. A silicon oxide layer has a specific dielectric constant of about 3.7 to about 4.0 such that the silicon oxide layer is advantageously used as the insulating interlayer.
The insulation layer including oxide is commonly formed using a spin-on-glass (SOG) based material such as hydro-silsesquioxane (HSQ) or methyl-silsesquoxan (MSQ), organic polymers, silicon oxycarbonate (SiOC), and other suitable materials. An SOG-based oxide layer has some disadvantages such as a relatively low dielectric constant and poor density. Thus, it is impractical to form a contact hole or a trench through the SOG base layer since the SOG base layer is readily etched during an etching process. In addition, moisture and contaminants may be readily permeated into the SOG based layer in the case where the SOG based layer is not completely cured under a subsequent curing process after forming the SOG based layer.
A silicon oxycarbonate SOG layer may be formed using methyl-silsesquioxane (MSQ) in a spin coating process. A silicon oxycarbonate layer may also formed by a plasma enhanced chemical vapor deposition process using a source gas, a reaction gas including oxygen and a carrier gas including nitrogen (N2), ammonia (NH3), helium (He) or argon (Ar). The silicon oxycarbonate layer has a specific dielectric constant of about 2.7 to about 2.9 and a parasitic capacitance that is relatively lower than that of the silicon oxide layer by about 25 to about 30 percent. However, the silicon oxycarbonate layer is limited by several disadvantages as follows.
When forming the silicon oxycarbonate layer, a footing of a photoresist pattern may be generated when the photoresist pattern is formed on the silicon oxycarbonate layer. In addition, the silicon oxycarbonate layer has poor mechanical strength so that micro-scratches and exfoliation may be frequently generated on the silicon oxycarbonate layer when a trench is formed through the silicon oxycarbonate layer by etching the silicon oxycarbonate layer and forming a metal wiring structure in the trench by a chemical mechanical polishing (CMP) process.
To overcome the above-mentioned limitations, a method of forming a thin capping layer on the silicon oxycarbonate layer has been developed. The object of the capping layer is to prevent damage to the silicon oxycarbonate layer during the CMP process. However, when the capping layer is formed on the silicon oxycarbonate layer using a source gas including tetraethylorthosilane (TEOS) by a PECVD process, the capping layer may not be uniformly formed on the silicon oxycarbonate layer or the capping layer may be lifted from the silicon oxycarbonate layer because the capping layer may not be sufficiently adhered to the underlying silicon oxycarbonate layer. FIG. 1 is an electron microscopic picture illustrating a silicon oxycarbonate layer and a capping layer formed in accordance with the conventional approach. Furthermore, since an interface is generated between the capping layer and the silicon oxycarbonate layer, cleaning solution may permeate into the interface, thereby causing damage to the silicon oxycarbonate layer. Also, leakage current may be generated at the interface between the capping layer and the silicon oxycarbonate layer.